Superjunction devices exploit the idea to compensate surplus charges in the on-state current path by adding charges of the opposite polarity in the vicinity of this area to achieve very low area specific RDSon values. Typical constructions for vertical devices use vertical n- and p-doped columns which are formed either by trench etching and refill or by multi epitaxial arrangements.
This very low specific RDSon values enable very small device areas (w/r to standard MOSFETs) leading to very fast switching devices (low capacitances CGD, CGS, CDS). Fast switching is the basis for very low switching losses for example in switch mode power supplies which had boosted their efficiency significantly in recent years.
To have sufficient noise immunity state of the art superjunction devices have stayed with gate threshold voltage in the range of 3.5V to 5V reaching full turn-on with Gate voltages around 10 to 12V.
This hampers further efficiency improvements as switching speed and therefore switching losses are closely linked to the voltage swing needed for full turn-on.
Drawbacks of the existing solutions with Vth >3.5V are:                higher switching losses than with lower gate threshold voltage.        higher driving losses; devices with lower gate threshold voltage can be driven by the same driving current much faster or with the same speed with less driving power.        state of the art power devices can't be driven directly with TTL or CMOS stages; they need a booster/level-shifter stage.        
FIG. 2a shows state of the art PFC (Power Factor Correction) stage 20 using a power MOSFET 22 having a normal level threshold voltage, e.g., Vth=3V to 5V. This solution needs after the controller 24 generating the PWM for voltage/current control an additional booster stage 26 which generates gate voltages for the power MOSFET 22 in the range of 10V to 15V with an appropriate current level. Despite the additional booster stage 26 this solution usually needs an additional voltage domain (e.g., 20V to 30V) to supply the booster 26 and support the driving of the power MOSFET 22. However this means additional effort either in terms of additional device cost, area, and higher losses.
A similar example is shown in FIG. 3a. FIG. 3a shows a Flyback topology 30 which uses state of the art a power MOSFET 32 having normal level threshold voltage, e.g., Vth=3-5V. This solution needs after the controller 34 generating the PWM for voltage/current control an additional booster stage 36 which generates gate voltages for the power MOSFET 32 in the range of 10V to 15V with an appropriate current level. Despite the additional booster stage 36 this solution usually needs an additional voltage domain (e.g., 20V to 30V) to supply the booster 36 and support the driving of the power MOSFET 32. However this means additional effort either in terms of additional device cost, area, and higher losses.
Therefore, there is the need for a structure having lower logic level threshold voltage at the same time having sufficient noise immunity.